It has become more common to provide multiplier circuits on programmable logic devices, rather than requiring users of such devices to construct multipliers from the available programmable logic resources. However, a multiplier circuit consumes a relatively large area, and its inputs can consume significant routing resources.
For example, multipliers are provided to multiply m bits by n bitsxe2x80x94e.g., 18xc3x9718 bits (frequently m=n). However, a user of the programmable logic device might have need of a p-bit by q-bit multiplier, where p and q are chosen by the user at the time of programming and may be different in every case, and p less than m and q less than n. This can be accomplished during programming by pre-loading or padding the unused bits with zeroes. However, the inputs to those unused bits have to be driven by a source, and the source has to be routed to the inputs. Therefore, padding the unused bits consumes resources which then are unavailable for other uses, even though the inputs remain constant throughout device operation.
Alternatively, additional registers could be provided and ANDed with the multiplier input registers, and each additional register could be set to either one (this would be the case for the most significant multiplier bits, which will be used) or zero (in the case of the least significant multiplier bits, which will not be used). Whether a particular register was set to zero or one could be controlled by configuration bits. While this consumes fewer resources than routing the zeroes directly to the less significant multiplier inputs, it still requires providing additional registers and configuration bits.
In another example, a multiplier might be used in a configuration in which one of its inputs is a constant coefficient, again consuming routing resources for the constant coefficient. Indeed, one such use is in a finite impulse response (FIR) filter, which requires several multipliers, compounding the use of routing resources. Moreover, in such a filter, the outputs of the various multipliers must be accumulated by a plurality of adders, consuming further routing resources to direct the various products to the adders and the sums to other adders.
It would be desirable to be able to provide programmable logic devices with multiplier circuits, where those multiplier circuits are configured to reduce resource utilization.
It is an object of the present invention to provide programmable logic devices with multiplier circuits, where those multiplier circuits are configured to reduce resource utilization.
In accordance with the present invention, there is provided a programmable logic device comprising a multiplier circuit, which may be that described in copending, commonly-assigned U.S. patent application Ser. No. 09/924,354, filed Aug. 7, 2001, which is hereby incorporated by reference in its entirety. The programmable logic device includes a plurality of scan chain registers for testing purposes, and at least a portion of the plurality of scan chain registers are located adjacent the multiplier circuit. Input circuitry is provided for using data in the scan chain registers to modify input data to the multiplier circuit.
In accordance with one aspect of the invention, the multiplier circuit, which can multiply two numbers having m and n bits, respectively (frequently, m=n), can be configured to multiply instead pxc3x97q bits, where p less than m and q less than n. (frequently, p=q). This is known as subset multiplication, and the multiplier is known as a subset multiplier. To avoid wasting routing resources to pad the inputs with zeroes to account for the missing mxe2x88x92p bits and the missing nxe2x88x92q bits, the scan chains normally provided for testing of the programmable logic device are used.
Scan chains typically are provided throughout a programmable logic device for testing purposes. After the device is manufactured, a predetermined pattern of ones and zeroes is clocked through the scan chains and the progression of that pattern through the chain, which has registers throughout all parts of the device, is checked. If there is any deviation from the input pattern, that indicates a potential manufacturing flaw, which can be isolated by determining where in the chain the pattern becomes corrupted.
In accordance with this aspect of the invention, scan chain registers adjacent the multiplier inputs are ANDed with the multiplier inputs. The scan chain registers corresponding to the least significant mxe2x88x92p and nxe2x88x92q bits of the multiplier inputs are loaded, after device testing, with zeroes, while the p and q most significant bits are loaded with ones. Because no further data are input to the scan chain registers, they retain the values loaded into them throughout device operation. ANDing the scan chain registers, loaded with ones and zeroes as described above, with the multiplier inputs has the same effect as padding the least significant bits with zeroes, but without using routing resources. Thus, the routing resources connected to the least significant bits of the multiplier inputs can be used for other functions, because it does not matter for multiplication purposes what values appear in those bits, which will always be ANDed with zeroes. Because the remaining bits of the scan chain registers are loaded with ones, the values in the most significant bits of the multiplier inputs pass through the AND operation to the multiplier. Normally, the multiplier inputs are registered (synchronous input), and the scan chain registers are ANDed with the input registers. Sometimes, however, the multiplier inputs are asynchronous and not registered, in which case the scan chain registers are ANDed with the inputs themselves.
In accordance with another aspect of the present invention, there is provided a programmable logic device comprising a plurality of multiplier circuits arranged in a logic block. The logic block further comprises a plurality of adders for accumulating outputs of the plurality of multiplier circuits, as described in copending, commonly assigned U.S. patent application Ser. No. 09/955,645, filed Sep. 18, 2001, now U.S. Pat. No. 6,538,470, which is hereby incorporated by reference in its entirety. The multipliers and the adders in the logic block are configured for various uses, including formation of a finite impulse response filter.
In accordance with this aspect of the invention, the finite impulse response (FIR) filter may be a xe2x80x9cDirect Form Ixe2x80x9d FIR filter or a xe2x80x9cDirect Form IIxe2x80x9d FIR filter. Either type of FIR filter requires, in addition to the multipliers and adders, registers for registering either input data (samples) or intermediate data, with the number of registers preferably equaling the number of multipliers in the FIR filter. In the case of a Direct Form I FIR filter, the registers are at the outputs of the multipliers, while in a Direct Form II FIR filter, the registers are at the inputs of the multipliers.
In either type of FIR filter, one of the inputs to each multiplier sometimes is a coefficient fixed at the time of programming and specific to the use that will be made of the filter, although in other cases, such as in an adaptive FIR filter, the coefficients may vary over time. Because the coefficient may be fixed, it would be a waste of routing resources to consume those resources with the values for the coefficients. Therefore, as discussed above in connection with subset multipliers, in accordance with this aspect of the invention, the scan chain registers that are ANDed with the multiplier coefficient inputs are loaded with the filter coefficients after testing of the device is complete.
In a variant of this aspect of the invention, the scan chain registers are also used for the data (sample) inputs to the FIR filter. This is accomplished by ANDing other scan chain registers to the other inputs (or input registers) of each multiplier, and then clocking data through the scan chain during use to provide the filter sample inputs. If this variant is used, then a way must be provided to prevent the coefficient data in the scan chain registers, which are supposed to be fixed, from being clocked through the scan chain as the input sample data are clocked through. This is preferably accomplished using one or both of two methods.
The first method to prevent coefficient data from being clocked through the scan chain as the input sample data are clocked through is to provide in the scan chain one or more switches or links that can be opened after the coefficient data are loaded into the appropriate scan chain registers. Opening the link or switch would then isolate those registers from the remainder of the scan chain, so that the input sample data are not clocked through into the coefficient registers. This requires arranging the scan chain so that all of the scan chain registers to be used for coefficient data are downstream of any scan chain registers to be used for input sample data.
The second method to prevent coefficient data from being clocked through the scan chain as the input sample data are clocked through is to provide a first coefficient clock for those scan chain registers that are to be used for coefficient input, and a second separate data or sample clock for the other scan chain registers, including those to be used for sample data input. The two clocks would be connected, or run in synchrony, during xe2x80x9cnormalxe2x80x9d scan chain testing operation and clocking in of the coefficient data. The coefficient clock would then be disconnected from the sample data clock or simply turned off, and preferably grounded, to prevent alteration of the coefficient data even though the coefficient registers remain connected to the scan chain and data is being clocked through any registers clocked by the data or sample clock. This still requires arranging the scan chain registers in the correct order with foreknowledge of which will be used for coefficients, so that all coefficient registers are downstream from all sample data registers, because even though the coefficient registers are not removed from the chain as in the previous embodiment, no data will be able to be clocked through the coefficient registers to downstream sample data registers. This also requires using the same foreknowledge to connect the correct clock to each scan chain register. This second method may be, and preferably is, used in conjunction with the first method.
For some applications, such as in adaptive FIR filters, it may be desirable or necessary to change coefficients on the fly, or at least occasionally, during operation of the device. The use of scan chains to load coefficients facilitates such on-the-fly changes. Thus, in an embodiment where the coefficients are loaded using a separate scan chain with its own clock, the clock can be restarted whenever it is desired to change the coefficients. In an embodiment where the samples and coefficients are loaded using the same scan chain, which is then broken after the coefficients are loaded, when it is desired to change the coefficients the break must be closed (as by a switch). In the latter embodiment, there will be a period, while the new coefficient data propagates through the sample portion of the chain, that the filter output is not meaningful.
Separate and apart from the use of scan chain registers as coefficient and/or sample data inputs to a FIR filter, the logic block described above including multipliers and adders that can be configured as a FIR filter includes the routing necessary to connect those elements as a FIR filter, relieving the load on the general routing of the programmable logic device. Thus, the logic block, which may be referred to as a multiplier-accumulator (MAC) block or, because it is frequently used in digital signal processing, a DSP block, includes multipliers, adders, registers in the two different locations required for the two different types of FIR filters, as discussed below, and multiplexers for selecting between the two configurations, again as discussed below.